Upgrading your hardware - a case study 2014 Jun 18
The IS5 processor board was the fifth incarnation of a general purpose processor board for the Inventio range of products. It started out as the brains for the "Titrette" Karl Fischer titrator (1999) - yes this was in the last century. Since then it has had minor improvements and changes to the mounting holes, ending up as the IS5c (2008), for the Conveyor Belt computer.
Following the maxim “if it ain’t broke, don’t fix it”, when it came to the IS5d (2014) we kept as much as possible the same. Plated through hole components were replaced by surface mount (SM), the two layer board became a four layer (because you can’t get a track between SM pins), and this allowed a proper ground and power plane, and makes the signal tracking cleaner.
The switched mode power supply chip, capacitors and inductor got smaller, due to improvements in the technology, and the LCD is now mounted on the component side of the board. The mounting holes now fit the custom enclosure for the Conveyor Belt Computer, CBC-02.
But some things have remained the same : still an 8051 processor, but now with 64K on-chip FLASH memory, and a boot-loader program built in. No more ultra-violet erasing and EPROM programming. In its day the UV erasable EPROM was fantastic - no more 6 month wait for a masked ROM with no possibility of changing it! But I’m talking 1979 here, and now we have FLASH technology, so no more 10 minute wait while the EPROM erases, and 30 seconds to reprogram and replace the chip. Phew.
We have kept a 32 pin socket for an EPROM. Sometimes you want an unskilled operator to do a field upgrade - the EPROM can be sent by post and plugged in.
So why not an ARM? There are hidden costs in unnecessary complexity. The ARM architecture has evolved to maximise performance in a mobile phone or tablet - clock frequencies and power consumption are higher, noise immunity is lower. The 8051 is very simple, and with the souped-up versions now available is plenty fast enough for the sort of applications we are targeting. But the biggest problem for me in using an ARM chip is that you are heading in the direction of Linux. Don’t get me wrong - I have nothing against either ARMs or Linux - but we are not running a web browser here - just an ultra reliable data cruncher.
The IS5d hardware and software work together - if the power goes down an interrupt gives you at least 50 ms warning, plenty of time to save data to EEPROM, log the event and wait for the power to go on again, all in an orderly fashion. Likewise a noise spike may crash the system, especially in a hostile environment such as a rock quarry, the watchdog timer will restart the program after 200 ms.
We have kept the 32K bytes of battery backed RAM - why not EEPROM or FRAM? Its nice to have such a lot of memory, we need a battery for the Real Time Clock anyway, so its minimal extra cost. Critical data is backed up by having two copies, each with a CRC checksum, and this provides a solution to the problems of “tearing” (to use a smart card term), when the power plug is pulled without warning. Some of these units are powered from a diesel engine’s battery - the voltage when somebody starts the engine can be somewhat erratic. With a power fail interrupt, plus the backup copy, plus a log of any errors, we know that we don’t get errors. Serial FRAM is quick, but not as quick as parallel SRAM, so timing becomes more critical, and the backup checks more complicated, and more difficult to test.
And of course there is the software : Forth. A cooperative multi-tasker, with the measurement task activated by a precise 200 ms timer interrupt. Keypad and UART events are interrupt driven, so we never lose a key press and the text display update is snappy. There is no hourglass to wait for… There are no rare timing events that you can get with a pre-emptive multi-tasker, just a handful of tasks, some running when they can, some tightly timed.
One of the tasks handles the serial port handshaking - if you unplug the printer the printer task waits, queuing the data until you plug it in. The handshake line is debounced for a second to make sure the printer really is plugged in, then printing continues.
Each of these features has developed over time - 16 years - and when considering the next evolution of hardware it is important not to throw away this development effort. It is very time-consuming to re-develop all of these features for a new processor, and even more time-consuming to test that everything works.
So that’s why we kept the 8051. For a battery powered project, the Sinar Ceres, we used the MSP430, because it needed USB and low power - maybe we will need an ARM someday.
For now, the IS5d is the simplest possible solution to the current batch of requirements.
Howerd Oakford 2014 Jun 18
The IS5 processor board was the fifth incarnation of a general purpose processor board for the Inventio range of products. It started out as the brains for the "Titrette" Karl Fischer titrator (1999) - yes this was in the last century. Since then it has had minor improvements and changes to the mounting holes, ending up as the IS5c (2008), for the Conveyor Belt computer.
Following the maxim “if it ain’t broke, don’t fix it”, when it came to the IS5d (2014) we kept as much as possible the same. Plated through hole components were replaced by surface mount (SM), the two layer board became a four layer (because you can’t get a track between SM pins), and this allowed a proper ground and power plane, and makes the signal tracking cleaner.
The switched mode power supply chip, capacitors and inductor got smaller, due to improvements in the technology, and the LCD is now mounted on the component side of the board. The mounting holes now fit the custom enclosure for the Conveyor Belt Computer, CBC-02.
But some things have remained the same : still an 8051 processor, but now with 64K on-chip FLASH memory, and a boot-loader program built in. No more ultra-violet erasing and EPROM programming. In its day the UV erasable EPROM was fantastic - no more 6 month wait for a masked ROM with no possibility of changing it! But I’m talking 1979 here, and now we have FLASH technology, so no more 10 minute wait while the EPROM erases, and 30 seconds to reprogram and replace the chip. Phew.
We have kept a 32 pin socket for an EPROM. Sometimes you want an unskilled operator to do a field upgrade - the EPROM can be sent by post and plugged in.
So why not an ARM? There are hidden costs in unnecessary complexity. The ARM architecture has evolved to maximise performance in a mobile phone or tablet - clock frequencies and power consumption are higher, noise immunity is lower. The 8051 is very simple, and with the souped-up versions now available is plenty fast enough for the sort of applications we are targeting. But the biggest problem for me in using an ARM chip is that you are heading in the direction of Linux. Don’t get me wrong - I have nothing against either ARMs or Linux - but we are not running a web browser here - just an ultra reliable data cruncher.
The IS5d hardware and software work together - if the power goes down an interrupt gives you at least 50 ms warning, plenty of time to save data to EEPROM, log the event and wait for the power to go on again, all in an orderly fashion. Likewise a noise spike may crash the system, especially in a hostile environment such as a rock quarry, the watchdog timer will restart the program after 200 ms.
We have kept the 32K bytes of battery backed RAM - why not EEPROM or FRAM? Its nice to have such a lot of memory, we need a battery for the Real Time Clock anyway, so its minimal extra cost. Critical data is backed up by having two copies, each with a CRC checksum, and this provides a solution to the problems of “tearing” (to use a smart card term), when the power plug is pulled without warning. Some of these units are powered from a diesel engine’s battery - the voltage when somebody starts the engine can be somewhat erratic. With a power fail interrupt, plus the backup copy, plus a log of any errors, we know that we don’t get errors. Serial FRAM is quick, but not as quick as parallel SRAM, so timing becomes more critical, and the backup checks more complicated, and more difficult to test.
And of course there is the software : Forth. A cooperative multi-tasker, with the measurement task activated by a precise 200 ms timer interrupt. Keypad and UART events are interrupt driven, so we never lose a key press and the text display update is snappy. There is no hourglass to wait for… There are no rare timing events that you can get with a pre-emptive multi-tasker, just a handful of tasks, some running when they can, some tightly timed.
One of the tasks handles the serial port handshaking - if you unplug the printer the printer task waits, queuing the data until you plug it in. The handshake line is debounced for a second to make sure the printer really is plugged in, then printing continues.
Each of these features has developed over time - 16 years - and when considering the next evolution of hardware it is important not to throw away this development effort. It is very time-consuming to re-develop all of these features for a new processor, and even more time-consuming to test that everything works.
So that’s why we kept the 8051. For a battery powered project, the Sinar Ceres, we used the MSP430, because it needed USB and low power - maybe we will need an ARM someday.
For now, the IS5d is the simplest possible solution to the current batch of requirements.
Howerd Oakford 2014 Jun 18
