Chuck Moore's VLSI Chip and Transistor Simulator

# Simulation

Armed with transistor and net tables, the program can simulate the chip. It applies 5 Volts to the power pins and computes the consequences. There is no need for the elaborate procedure used by SPICE. Simply integrate the set of differential (difference) equations with integer arithmetic using the indicated units:

         equation            units
         dQ = I(V,T) dt      aC = uA ps
         V = Q/C             mV = aC/fF
         dT = f(T-Te) dt     uK

First compute the current thru each transistor, adjusted for temperature. Add the resulting charge to input and output nets. Change the temperature depending on the amount it differs from power equilibrium. Then compute the voltage on each net from its charge and capacitance. Repeat indefinitely.

## Transistors and nets

The first step in simulating a layout is to identify the transistors and the nets by which they're connected. The i21st has 16,000 transistors and 5000 nets (roughly 3 transistors/net). Each transistor is characterized by a drive and each net by a load.

To speed net identification, the program first traces the largest nets, core power and ground. It starts at the input pad and uses a recursive algorithm to follow the trace through metal and diffusion, branching as required. It marks each tile with a flag:

         01 - power
         10 - ground
         00 - neither

It then scans the poly layer and locates transistors where poly crosses diffusion. It measures their size by following the poly trace. It then identifies the nets for source, gate and drain. It can distinguish source and drain only when source is core power or ground. The result is 2 tables:

           TRAN: +0  Source net index
                 +2  Gate net
                 +4  Drain net
                 +6  Drive (uA)
       LOCATION: +0  Lower-left gate tile

To identify a net that is not power or ground, it follows the trace, recursively when it forks, changing layers as needed. It does 2 things:

1 - Computes capacitance (to substrate) depending upon the layer:

         diffusion  3 fF/tile
              gate  5
              poly  .4
             metal  .3
           metal-2  .5

These numbers can be calculated from process parameters, but are best measured by an on-chip test circuit.

2 - Looks for a tile bit indicating the 'owner' of the net. If it finds an owner bit while on a plausible layer, it searches an 4-byte table to identify the net:

        ANCHOR: +0  Location of owner
           NET: +0  Capacitance (fF)
                +4  Coupled charge (aC)

The net is the one whose location matches the current position.

Lacking an owner indicates a new net. An entry is created, with the owner being the location the search was started. The layer is important. For example, a metal trace might cross a poly owner, yet be on a different net. Since the owner bit does not identify the layer, it is determined by these rules:

         Not metal-2
         Not metal if over poly or diffusion

Transistor gates are owned by poly, source or drain by diffusion. Pads are owned by metal.

A table of coupling capacitance is constructed:

         G_D: +0 Gate net
              +2 Drain or source net
              +4 Capacitance

Transistors with the same gate and drain are combined (inverters) and only significant coupling retained.

Clearly this process takes some time (10 s). A scan of the entire layout looks for transistors. Another scan looks for resistors. These are drawn as a 1-tile wide, vertical n-well.

## Integration

2 arrays are used to store current values. For each net:

         IV: +0 Voltage (mV)
             +2 Previous voltage
             +4 Charge (aC)

For each transistor:

         TK: +0 Temperature (uK, actually 2*20)
             +4 kS (um)

### Current

For each transistor, current is computed from gate, source and drain voltages. It's corrected for temperature by a table-lookup for the factor

         (Ta/T)*1.5

Chip temperature is only 2 K above ambient, which may be specified (298 K). This current times 7.8 ps is the charge added to the drain net and subtracted from the source net. The current thru a p-transistor is negative.

### Temperature

Current is multiplied by voltage across the transistor to get power (p). This is summed for all transistors to get total chip power. It is also used to compute an equilibrium temperature proportional to energy density

         Te = (p dt)/kS

If temperature is below equilibrium, it is approached exponentially, increasing by

         a (Te-T)

If above, it is decreased by

         b (T-Te)*3

This approximates diffusion decay of t*.5 (square-root time). Coefficients a and b must be measured. Temperature rises rapidly (ps) and falls slowly (ns).

### Coupling

The effect of coupling capacitance is to change the charge and thus the voltage on both nets. The equations for drain to gate are:

         Qd = Vd Cd + (Vd-Vg)Cgd
         Vd(Cd+Cgd) = Qd + Vg Cgd

So to the drain charge we add the gate voltage times the coupling capacitance. And conversely. Scanning the coupling table applies all significant effects. Coupling charge must be stored separately from net charge since it changes independently. Several gates may contribute to the same drain.

### Voltage

Finally, a voltage is computed for each net by dividing charge (plus coupling charge) by capacitance. This is extrapolated by using previous voltage, to the time for the next current calculation. In fact, this extrapolation leads to instability in small-capacitance nets and is neglected.

The time step of 7.8 ps resulted from the plotting convenience of 4x32 steps to 1 ns. It can't be larger because of small-capacitance voltage instability. To avoid most of these, series transistors are specially treated. There remain the internal nets of Schmitt inverters and some others.

## Transistor model

The transistor model evolves toward increased accuracy. The current model is described here. Basically source-drain current is a function of source, drain, gate and body voltages

         Ids = f(Vd,Vs,Vg,Vb)

variations of the Ebers-Moll model are usually used by SPICE simulators. But this model is too elaborate to calculate for 10,000 transistors. We use a 3-parameter empirical model adjusted to fit the measured Ids curves for a particular process. Even this model is best computed by table-lookup, inorder to minimize computation time.

The first approximation is to write the current as a product

         Ids = D(Vd,Vs)G(Vg)

This separation is not strictly accurate, but close enough. Body voltage is +0 for n-transistors and +5 for p-. It has no other function.

The IV curves look like this for a 1-tile n-transistor. The green curves are D vs Vd for Vg = 1, 2, 3, 4 and 5 V. The red curve is G vs Vg. Although the green curves should run to 5 V, we can't measure them. All available information is provided and the leaf-like symmetry is attractive.

The black dots are measured values. The green curves have been corrected for temperature and represent cold a transistor. The difficulty in relating dots to curves emphasizes the huge difference temperature makes.

The IV curves for a 2-tile p-transistor. It suggests that 3-tile transistors would better match the n-transistor curve. The dots show the p-transistors less affected by temperature, because of their lower current density.

G is computed by a clumsy exponential converging to linear. It is best considered a table look-up of the red curve. There are 300 values between 0-6 V at 20 mV increments.

D is computed as the parallel combination of 2 linear functions. Again, it is a table look-up with the same characteristics as G. Vs is +0 (or +5).

When Vs is not the same as Vb, SPICE includes a "body effect" correction. A more accurate treatment of this effect is to observe that

         Ids = Id0 - Is0

Thus the form used becomes

         Ids = (D(Vd)-D(Vs))G(Vg)

This product form can be effectively used to compute the current thru series transistors.

## Interconnect

### Gate capacitance

The largest MOS capacitance. It has plate and edge contributions. Also a voltage dependence: low capacitance till threshold. However, a simple average capacitance per tile is an adequate approximation. If Vdd varies from 3-5 V, a linear variation can be added.

### Trace capacitance

A much smaller MOS capacitance to substrate. Voltage dependence is ignored. There is plate capacitance determined by area, and edge capacitance determined by length. Their contributions are roughly equal in size and relatively insensitive to shape (straight, corner, tee, contact). The combination is even insensitive to trace width. It is approximated by an average capacitance per tile.

### Cross capacitance

Coupling between traces is neglected.

### Diffusion capacitance

Has plate and edge contributions, and a different and smaller voltage dependence. It is approximated by an average capacitance per tile. A linear variation with Vdd is added if 3-5 V range is required. p-diffusion is larger than n- by about 50%.

### Measured capacitance

Is provided by some fabricators. It agrees with calculations to 10%. However, measurements with our on-chip test circuit differ by 20%.

### Resistance

As with any model, unnecessary detail is ignored. Thus, trace resistance is neglected relative to a transistor:

         Polysilicon    80 Ohms/tile
        Polysilicide     8
         n-diffusion    35
         p-diffusion    70
               metal      .02
              n-well   700
          transistor  5000

Non-metal traces must be kept short enough that this assumption is valid.

## Inverter

This is a portion of the screen shown when an inverter is simulated. The lower trace is input, the upper is output and at the top is the output vs input voltage plot. The dark rectangle is 2 ns wide by 2.5 V high.

There are several interesting features in this display. Note the output is delayed from the input, perhaps 200 ps. The rise/fall time of the output is faster than the input. The output load is small enough that the inverter has some gain (in this sense).

The output vs input plot shows considerable hysteresis. This is typical of these relatively small gates. It's due to the fast transition and the time required to charge the output capacitance. The curve is not symmetrical because of the difference between n- and p-transistors. Textbooks don't include these effects.

The slight rise just before output falls is due to gate-drain capacitance. It is so small as to be negligible, as is its effect on rise/fall time. SPICE models claim a larger effect.