colorForth VLSI Design Tools

Updated 2001 June
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# VLSI Design Tools

In 500 lines of colorForth these tools provide everything required to design a chip. They are derived from an earlier version called OKAD that successfully generated many versions of Forth microprocessor chips.

# Description

A chip requires the placement and interconnect routing for a heirarchy of gates, cells, pads and floorplan. This is described using a coarse-grid coordinate system of boxes called "tiles". Each tile has 6 layers and can describe a trace, contact or transistor. Tile size is chosen to enforce the geometric design rules for a particular process.

A language for describing this is carefully designed to translate easily into GDSII. It includes positioning wells and diffusion, placing polysilicon to form a transistor, adding contacts to source and drain and routing traces amongst layers. This is a geometric description of a chip, including more information than a schematic provides.

# Gates

The gate library is where it starts. Several tiles are combined to construct a gate. Multiple gates form modules and multiple modules the chip. Basic gates are listed, with example descriptions and layout.

# Layout

The description is compiled and executed to construct a flat layout of a module, or the entire chip. This requires megabytes of RAM. The layout may be displayed in 2 or 3 dimensions at any magnification. It is examined for a design-rule-check. From it are extracted a list of transistors and a list of interconnect nets.

# Simulation

A transistor's current depends on the voltage of input, output and gate nets. And also upon channel width and temperature. The Simulator uses the transistor and net lists. Power is applied to the appropriate nets and the current through each transistor is computed. This changes the charge on the drain net and the temperature of the transistor. Voltage is computed from the net charge and capacitance. This repeats with a time step of 1 ps.

# GDSII

Compiling the description in a special context generates a standard GDS file instead of the layout. It takes no time and is accurate because of the one-to-one correspondance between Forth and GDS code.