Updated June 2001

# Layout

The chip description is used to fill an array of tiles. For example, the i21st microprocessor die is 3.3x4.1 mm. It requires a 1250x1562 array of 2.6 um tiles. Each tile uses 1 32-bit word of memory, so the chip is described in 7.8 Mbytes.

# Layers

14 bits are sufficient to describe the 6 layers of a 1-poly, 3-metal process. N-well is indicated by 1 bit. Metal-1 by 2. Diffusion, poly, metal-2 and metal-3 each use 3. 5 other bits are used for housekeeping.

Of the 3 bits, bit 0 indicates a horizontal trace extending from the center of the tile to to the center of the tile to its right. Bit 1 a vertical trace going up. Bit 2 a contact. All 8 combinations are possible in the same tile. Metal-1 does not need the contact bit. Any contact on diffusion, poly or metal-2 implies a contact on metal-1. Likewise, a contact on metal-3 implies one on metal-2.

Diffusion is different. The kind (n+ or p+) depends on the n-well bit. Bit 0 indicates diffusion (p+ in n-well, n+ over substrate), which fills the tile. Bit 1 indicates a contact. Bit 2 a well/substrate contact (reverse diffusion: n+ in n-well, p+ over substrate). The actual assignment is:

- 0 no diffusion
- 1 diffusion
- 2
- 3 diffusion contact
- 4
- 5 substrate contact
- 6
- 7 diffusion contact ignored during net extraction

Type 7 is needed to avoid a loop when recursively tracing paths between multiply-connected metal and diffusion.

These bits are formatted in a 32-bit word:

bit |  |  | 16 |  |  |  |  |  |  | 0
|  | 21p | s | o | 333 | 222 | 11 | ppp | ddd | w

with:

- w well
- ddd diffusion
- ppp poly
- 11 metal
- 222 metal-2
- 333 metal-3
- o net owner
- 21p brightening bits

The display provides 1024x768 pixels with 16-bit colors. A few of these are used:

- n-well yellow
- diffusion green
- poly red
- metal blue
- metal-2 silver
- metal-3 cyan

Bright and dark shades of red, blue and silver identify nets above and below .9 V. For example, bright red is poly at +1.8; dark red is poly at +0.

The layers are stacked in their physical order. They may be peeled off to examine detail otherwise concealed. Transparent colors are not helpful when looking 6 layers deep.

# Editing

The colorForth Editor is used to edit the chip description. The way gates are placed is determined by GDS. Basically it offers subroutines with 1 parameter, the position.

Routing is described by selecting a layer and distance left, right, up or down. It is somewhat clumsy, but translation to GDS restricts options. The Edit/Compile/Display cycle is so fast that immediate visual feedback is available. Running the simulator provides another check.

The advantage of such manual place and route is that you know what you get. If there is no room for a gate, or if a trace is unfortunately long, the layout can be reconsidered. Such an approach is required for sub-micron designs where interconnect capacitance becomes important. Multiple iterations approach the goal of a clear, modular, compact chip.

# Scaling

Each fabricator has a proprietary set of geometric design fules. These take the form of diagrams showing the size, spacing and overlap of each mask layer. To employ a process involves choosing the smallest tile size that conforms to the rules. Most rules are then satisfied by the discipline of the tiled layout. But all must be reviewed for exceptions.

Here are some typical parameters (um):

- .58 tile size
- .50 n-well overlap p-diffusion
- 1.0 n-diffusion to p-diffusion
- .18 poly width
- .25 poly spaceing
- .20 contact size
- .05 contact overlap
- .22 metal width
- .25 metal spaciang
- .28 metal-2 width
- .25 metal-2 spacing
- .25 via size
- 75 pad width
- 75 pad spacing
- 90 passivation

Most of these parameters are minima. But optimization requires they be followed as closely as possible. Safety factors have already been included.

Tile size has been limited by these constraints:

- Diagonally adjacent contacts are necessary for compact layout. Their minimum spacing is usually the limiting factor, probably in metal-2. This is most reasonably Euclidean spacing (along the diagonal). However sometimes Manhattan spacing is required.
- Poly spacing between abutting transistors.
- Gate layouts have 2 tiles between n and p diffusions.

Average current is limited by metal width:

- metal-1 0.5 mA/um
- metal-2 1.0
- metal-3 1.0

This is rarely a concern. Especially since peak current is reduced by the duty-cycle. However wide power and pad traces are required.