Chuck Moore's 25x Forth Multicomputer Chip

Updated 2001 June
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# 25x Microcomputer

An array of 25 microcomputers on a 7 sq mm die.

# Features

- .2 sq mm asynchronous microcomputer core
- 5 x 5 array of cores: 60,000 Mips
- 5 horizontal, 5 vertical parallel interconnect buses: 180 Ghz bandwidth
- Specialized computers to interface off-chip.
- Max power 500 mW @ 1.8 V, with 25 computers running
- 100mAh battery life is 1 year, with 1 computer running throttled
- 64-pin SOIC: mirrored pin-out to 4ns cache SRAM
- Array chips on 2-sided PCB

# Description

Availability of the tiny (.2 sq mm), asynchronous X18 microcomputer core naturally suggested arraying it on a chip. Its extremely low power (20 mW) made that feasible. A 5x5 array was chosen to fit on a 7 sq mm die, the smallest available prototype, though larger arrays are possible. 25 computers running at 2400 Mips is a total of 60,000 Mips. An unlimited supply.

Communication among the computers is provided by a network with 5 horizontal and 5 vertical buses. Each computer has 2 bus registers to access a horizontal and a vertical bus. Each bus is 18-bits wide and can run at 1 GHz. All 10 buses can be active at once connecting a 20-computer subset. So total bandwidth is 180 GHz.

Each computer can customized. Registers are added to the 16 processors at the edge of the array and connected to package pins. Each computer is responsible for a particular interface. Protocols are implemented with software.

- SRAM controller
- Flash controller
- 4 serial controllers
- USB controller
- D/A controller
- A/D controller

After booting from ROM, the computers await code downloaded from one of these interfaces.

# Pinout

Chosen to be the mirror image of an 18-bit cache memory chip. This is the fastest memory available, with 4 ns access. Its package is a 100-pin SOIC. The 18-bit Multicomputer thus has 256K words of external memory in 1 chip.

Putting the Multicomputer chip on the top of a 2-sided PCB and the SRAM chip on the bottom gives a very small footprint. A decoupling capacitor is the only other component needed. An array of such pairs is a multicomputer board. Connecting Multicomputer to SRAM is trivial, with mm traces. Routing for power and a serial network is also easy. Computers load code from the network.

A parallel computer with 60Gips nodes! Power is determined by the SRAM.

# Cost/Availability

The chip is awaiting funding. If interested, contact chipchuck@mindspring.com

A 7 sq mm die, packaged, will cost about $1 in quantity 1,000,000. Cost per Mip is 0.

25 prototypes can be obtained from MOSIS for $14,000 with 16 week turn-around. The TSMC .18um process has monthly submissions.